Muszę napisać licznik 4 bitowy na bazie przerzutnika T oraz bramki and. Muszę użyć 4 wyświetlaczy do wyświetlania stanu licznika. Tyle do tej pory udało mi się zrobić:
Kod: Zaznacz cały
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY licznik IS
PORT (ENABLE: IN STD_LOGIC;
RESET: IN STD_LOGIC;
CLOCK: IN STD_LOGIC;
o: OUT STD_LOGIC_VECTOR(3 downto 0));
END licznik;
ARCHITECTURE Behavior OF licznik IS
COMPONENT pT0 is
PORT (T,C,R : IN STD_LOGIC;
Q : buffer STD_LOGIC);
END COMPONENT;
COMPONENT AND0 is
PORT (X,Y : IN STD_LOGIC;
Z : OUT STD_LOGIC);
END COMPONENT;
COMPONENT dekoder is
PORT (
we: IN STD_LOGIC;
wy: OUT STD_LOGIC_VECTOR(6 downto 0));
END COMPONENT;
SIGNAL c1:std_logic;
SIGNAL c2:std_logic;
SIGNAL c3:std_logic;
SIGNAL c4:std_logic;
SIGNAL c5:std_logic;
SIGNAL c6:std_logic;
SIGNAL c7:std_logic;
BEGIN
M0: pT0 PORT MAP (ENABLE,CLOCK,RESET,c1);
H0: AND0 PORT MAP (ENABLE,c1,c2);
M1: pT0 PORT MAP (c2,CLOCK,RESET,c3);
H1: AND0 PORT MAP (c2,c3,c4);
M2: pT0 PORT MAP (c4,CLOCK,RESET,c5);
H2: AND0 PORT MAP (c5,c4,c6);
M3: pT0 PORT MAP (c6,CLOCK,RESET,o);
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pT0 IS
PORT (T,C,R : IN STD_LOGIC;
Q : buffer STD_LOGIC);
END pT0;
ARCHITECTURE Behavior OF pT0 IS
BEGIN
process (C,R,T)
BEGIN
if R= '1' then
Q<= '0' ;
elsif rising_edge(C) and T= '1' then
Q<= not Q;
end if;
END PROCESS;
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY AND0 IS
PORT (X,Y : IN STD_LOGIC;
Z : OUT STD_LOGIC);
END AND0;
ARCHITECTURE Behavior OF AND0 IS
BEGIN
Z<= (X AND Y);
END Behavior;