Kod: Zaznacz cały
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity modulo5 is
Port ( wyj : out std_logic_vector (3 downto 0);
clk : in std_logic);
end modulo5;
architecture Behavioral of modulo5 is
begin
abcd: process (clk) is
variable temp : unsigned (3 downto 0) ;
begin
if rising_edge(clk) then
temp := temp + 1 ;
end if;
wyj <= temp ;
end process abcd ;
end Behavioral;
Kod: Zaznacz cały
FATAL ERROR: VHDL Analyzer detecting a syntax error. Description of the error is:
modulo5.vhd(13): Syntax error at or near: is
Please correct this syntax error and try again...
ERROR: This design does not contain an entity named modulo5...
vhdtdtfi completed with errors...Proszę o pomoc.